The present invention relates to a computer that comprises a plurality of insertion cards or chips that are interconnected via a bus, wherein one insertion card includes a local processing unit and a first intermediate memory for intermediate storage of messages intended for the local processing unit, and a second intermediate memory for intermediate storage of messages originating from the local processing unit, wherein a third intermediate memory and a fourth intermediate memory are provided for free message locations that are intended for or originate from the local processing unit.
A computer having a plurality of local processing units is known from EP-A2-834 816, where the data transmission is effected via interface switching circuits that also take care of the assignment of the buses as operating means.
In many instances, however, it is necessary to transmit messages as data packets from one local processing unit to others, or from one local processing unit to the host or from the host to the local processing unit. A process for the transmission of data packets is known, for example, from EP-A2-817 095. With this process, the bus band width is to be increased in a multi processor system. For this purpose, additional bi-directional point-to-point connections of the individual local processing units are established. In addition, so-called repeaters are provided that make the appropriate messages accessible on the bus of all local processing units. Messages originating from one local processing unit are intermediately stored in an intermediate memory, while messages that are to be processed are conveyed directly to the local processing unit. In this connection, however, special precautions must be undertaken to ensure that the local processing unit, or possibly even the host, that sends the message does not become blocked due to errors during the acceptance of the message.
It has also already been proposed to limit the number of messages such that no overflow can take place. For this purpose, a list of free message locations is maintained, and a message can then be transmitted only if the number of cycling message records in the system are reduced by one. With this resolution, consistency with regard to the number of messages can be established.
It is also known to provide for respective intermediate storage of the messages and the free message locations in order to prevent blockage if a local processing unit is not immediately in a position to process an arriving free message location or an arriving message. This is particularly applicable if the intermediate memory or memories are realized in an integrated switching circuit, such as an ASIC, which although it enables a rapid triggering, the processing of the intermediate stored messages or the free message locations is effected in a non-synchronous manner, for example on a lower interrupt plane.
It is therefore an object of the present invention to provide a computer of the aforementioned general type that is particularly suitable for the exchange of messages between local processing units if the workload of the local processing units differs, without the danger arising that the overall capacity of the computer will be reduced by non-processed messages.